The present invention relates to chemical vapor deposition, integrated circuit fabrication and, in particular, to methods for depositing metal layers on a dielectric substrate.
Integrated circuits are fabricated by multiple processing steps which reproduce an array of identical electrically active devices and dielectric isolation regions on a semiconductor substrate or wafer. Active devices are electrically connected by contact structures that include multi-leveled metallization of conduction paths or interconnect lines. The multi-level metallization is formed by sequentially depositing layers of materials including an electrical conductor on a substrate, forming a patterned layer on the deposited layers, and etching the unprotected portions of the deposited layers to form the interconnect lines. The interconnect lines are electrically isolated by depositing an overlayer of an electrical insulator, such as a silicon oxide.
Copper is rapidly supplanting aluminum in the fabrication of interconnect lines because the use of copper enhances device performance and density at a reduced cost. The primary advantage of copper over aluminum is its significantly lower electrical resistivity. Because less power is dissipated by a material having a higher conductivity, integrated circuits having copper interconnect lines can operate at a significantly reduced power level. Further, the lower resistivity of copper reduces the delay in signal propagation associated with resistance capacitance (Rxe2x80x94C) effects. The higher electrical conductivity of copper also reduces the required number of interconnect levels, which eliminates a significant number of process steps and improves device yield. Finally, copper is less prone to the electromigration and stress migration that afflict interconnect lines of aluminum-based metallization. For all these reasons, multi-level interconnect lines of copper are now preferred in the fabrication of integrated circuits.
Despite these apparent advantageous material properties, copper-based interconnect lines have certain shortcomings, including but not limited to the significant diffusivity of copper in commonly-used dielectrics, such as silicon oxide. The presence of copper can cause the dielectric to become conductive and decrease the associated dielectric strength. Further, copper can diffuse through the dielectric layer to reach electrically active regions in the semiconductor substrate, such as a silicon substrate. Copper is known to be highly reactive with and a fast diffuser in silicon, in which copper acts as an impurity species to produce deep electron trap levels that negatively impact device performance and yield.
One known method of preventing copper diffusion into the dielectric and substrate is to position a barrier layer at the interface between the layers of copper and dielectric. For example, a barrier layer of a tantalum-based metal, such as tantalum (Ta) or tantalum nitride (TaNx), is commonly deposited to create a diffusion barrier between an interconnect layer of copper and an underlying dielectric, such as silicon oxide.
Various deposition and growth techniques exist for forming the tantalum-based diffusion barrier. For example, the barrier layer of tantalum or tantalum nitride can be deposited by a physical vapor deposition (PVD) technique, such as by sputtering. However, the resulting surface coverage is inadequate and non-uniform, particularly for surface features having a high aspect ratio, such as vias, contact holes, and trenches. Since sputtered material moves in line-of-sight paths to a substrate, a layer deposited by sputter deposition can not conform to the surface topography. Layers deposited by PVD have a thickness contingent upon the angle of exposure to the incident flux of deposition material so that the bottoms and sidewalls of high aspect ratio features are not effectively covered.
Chemical vapor deposition (CVD) processes, such as thermal CVD and plasma enhanced CVD (PECVD), provide deposition methods for tantalum-based materials that have important advantages over PVD. In particular, chemical deposition processes can synthesize a layer with significantly improved conformality so that the bottoms and sidewalls of high aspect ratio features are covered by nearly equivalent thicknesses of layer material.
Thermal CVD is a high temperature process in which gaseous reactants, which may contain a halogen-based vapor phase reactant, are passed over a heated substrate. The gaseous reactants readily decompose in the high temperature environment of the reactor and recombine to form a solid layer on the heated substrate. Plasma-enhanced CVD introduces a plasma to produce reactive chemical species from the gaseous reactants, which combine to deposit the desired layer on the surface of the substrate. The plasma enhancement provided by plasma-enhanced chemical vapor deposition allows layers to be deposited at a significantly lower temperature than those deposited by unassisted thermal chemical vapor deposition methods.
A tantalum-based material can be formed by a chemical vapor deposition process that exposes a heated surface of a substrate to a vapor-phase reactant of a tantalum halide, such as tantalum pentafluoride (TaF5), and a reducing gas, such as hydrogen (H2) or ammonia (NH3). Tantalum metal is deposited if hydrogen is used as the reducing gas, and tantalum nitride metal is deposited if ammonia or other nitrogen-containing gas is used as the reducing gas. Layers deposited by chemical vapor deposition processes incorporate, as an impurity, a low level of residual halogen atoms that originate as a by-product from the reduction of the metal halide vapor-phase reactant.
One drawback associated with the chemical vapor deposition of the tantalum-based layer on the dielectric is the presence of an enhanced concentration of residual halogen atoms at the interface between the dielectric and the metal layer. Particularly, the interfacial halogen has been found to correlate with reduced adhesion of the tantalum-based metal layer to the underlying dielectric. As a result, delamination of the metal layer is substantially more likely to occur. FIG. 1 is a secondary ion mass spectroscopy (SIMS) depth profile that shows the high level of fluorine trapped at the metal/dielectric interface following a deposition of a 20 nm layer of tantalum by PECVD on silicon oxide. The level of trapped fluorine can approach 5 atomic percent.
There is thus a need for a deposition method that will prevent extraneous halogen atoms from accumulating at the interface between a tantalum-based layer, deposited by a chemical vapor deposition process, and an underlying dielectric and that can do so without significantly altering the properties of a copper layer subsequently deposited over the tantalum-based layer.
The present invention provides a method of depositing a tantalum-based layer onto a dielectric-covered portion of a semiconductor substrate, wherein the layer has an enhanced adhesion to the dielectric. To this end, and in accordance with the principles of the present invention, a thin layer of silicon having a predetermined thickness of between about 1 nm and about 10 nm is formed on the dielectric before forming a superjacent layer of a tantalum-based material by chemical vapor deposition (CVD). By way of example, the tantalum-based layer may comprise either tantalum or tantalum nitride formed by any CVD method, such as either plasma-enhanced CVD or thermal CVD, utilizing a vapor-phase reactant of a tantalum halide, such as tantalum pentafluoride. The silicon layer prevents significant accumulation of by-product halogen atoms at the interface between the tantalum-based metal layer and the dielectric material. As a result, the silicon layer enhances the adhesion between the tantalum-based metal layer and the underlying dielectric that has been correlated with the absence of a significant concentration of halogen atoms at the metal/dielectric interface.
In one embodiment, the layer of silicon is a sacrificial layer that may be substantially removed from the surface of the dielectric during the CVD of the tantalum-based metal layer. As a result, the properties of the metal/dielectric interface are unaffected by the intervening silicon layer because it is no longer present.